A new technique for noise-tolerant pipelined dynamic digital circuits
نویسندگان
چکیده
Noise issues are becoming a main concern in digital systems due to the aggressive scaling trends in devices and interconnections. To address this problem in this paper we present a new noisetolerant dynamic circuit technique suitable for pipelined dynamic digital circuits. Simulation results for CMOS AND gate show that the proposed technique has an improvement in the ANTE of 3.4 over conventional dynamic logic. The improvement in the delayANTE quotient is 2.8 over conventional dynamic logic, 2.0 over Twin-Transistor technique [7] and 1.7 over Bobba’s technique [6]. A 4-bit full-adder simulated using the proposed technique improves ANTE by 2.1 over the conventional dynamic circuit.
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